SPEAKER_1: Alright, so last episode we landed on something important: Nvidia's rerating wasn't just about AI being exciting—it was about controlling a scarce enabling layer. But that immediately raises a question I want to press on. Nvidia designs the chips, but who manufactures them? SPEAKER_2: That's exactly the right next question. And the answer is TSMC—Taiwan Semiconductor Manufacturing Company. Nvidia is a fabless company, meaning it designs chips but doesn't own fabrication plants. TSMC is the foundry that manufactures chips for numerous designers who opt not to build their own fabs. SPEAKER_1: So the distinction is design versus manufacturing. Why does that split matter so much for understanding the AI supply chain? SPEAKER_2: Because it means the bottleneck can live in two completely separate places. Even with the best AI accelerator designs, if TSMC lacks the capacity to produce them at the required node, they can't be manufactured. Design and manufacturing are two different constraints, and they can bind independently. SPEAKER_1: Mm-hmm. And TSMC's position in this isn't just significant—it's dominant. What does the market share picture actually look like? SPEAKER_2: Concentrated to a degree that surprises most people. Counterpoint Research noted TSMC's foundry share increasing from around 62% in early 2024 to approximately 65% by mid-2024. TrendForce data for Q4 2024 shows TSMC holding about 67% of foundry revenue among the top ten foundries. Samsung, the next largest competitor, held a high-single-digit share. SPEAKER_1: So the gap between first and second place is enormous. SPEAKER_2: It's not a competitive market in the traditional sense. Samsung and Intel are both behind TSMC at the most advanced nodes—3 nm and below—which creates what analysts describe as a temporary single-supplier dynamic. Many leading-edge chip designs rely primarily on TSMC for volume production. There's no easy substitute. SPEAKER_1: Wait—so if you're a chip designer and you need 3 nm production, you're essentially negotiating with one counterparty? SPEAKER_2: For practical purposes, yes. And that's where the rerating logic kicks in. Think of it this way: Counterpoint and TrendForce both link TSMC's share gains directly to surging orders for AI GPUs and high-performance computing devices. When AI chip demand exploded, TSMC became the physical gatekeeper. The manufacturer became more strategically important than the brand-name designer during the shortage. SPEAKER_1: That's the counterintuitive point. The designer gets the headlines, but the manufacturer holds the actual constraint. SPEAKER_2: [emphasis] Exactly. And the constraint isn't just wafer fabrication. It extends into advanced packaging. TSMC's CoWoS—Chip-on-Wafer-on-Substrate—is the packaging technology that stacks memory alongside AI accelerators. TrendForce highlights ongoing CoWoS shortages since 2023, affecting both upstream equipment suppliers and downstream packaging materials. SPEAKER_1: So the bottleneck isn't one thing—it's wafer capacity and packaging capacity running tight simultaneously. SPEAKER_2: Right, and TSMC's own 2024 annual report reflects this. It describes continuous capital expenditure to expand both leading-edge wafer fabs and back-end services. The report also notes that TSMC accounted for about 34% of the broader Foundry 2.0 industry—which includes packaging, testing, and mask-making—up from 28% the prior year. That's not just a wafer business anymore. SPEAKER_1: For someone tracking this as an investment signal, what are the specific indicators that confirm a foundry rerating rather than just a cyclical uptick? SPEAKER_2: Five things to watch. Capacity utilization at advanced nodes. Revenue mix shifting toward 3 nm and 2 nm. Capex guidance—TSMC's own spending commitments signal how durable it believes demand is. Customer concentration, because when hyperscalers are competing for the same wafer slots, that's structural. And management commentary about lead times. TrendForce notes that because chip designs are finalized one to three years in advance, the current imbalance has locked in a period where TSMC is the critical bottleneck. SPEAKER_1: That lead-time point is striking. So customers are essentially reserving manufacturing capacity years before the chip even tapes out? SPEAKER_2: [short pause] Some analyses describe it as financializing manufacturing capacity itself—treating wafer starts as a scarce asset that investors and customers monitor as closely as chip architectures. Chip designers are securing TSMC slots far ahead of tape-out. That's a different kind of scarcity than a quarterly supply squeeze. SPEAKER_1: Now, what are the risks specific to a foundry rerating? Because the thesis sounds compelling, but there have to be pressure points. SPEAKER_2: Several. Semiconductor cyclicality is real—foundry demand can fall sharply when end markets slow. Geopolitical concentration is significant: TSMC's primary fabs are in Taiwan, which introduces risk that's hard to hedge. Capex intensity is enormous—smaller foundries struggle to justify the multi-billion-dollar investments required for advanced nodes, which is actually why TSMC's dominance keeps compounding. And customer dependence cuts both ways: if a major customer builds more in-house capacity, TSMC's utilization drops. SPEAKER_1: So the moat is real, but it's not frictionless. The geopolitical piece especially seems like something Trey Clark and anyone tracking this series should keep in the back of their mind throughout the season. SPEAKER_2: It's a thread that runs through multiple episodes. Now, the forward picture: TrendForce forecasts 3 nm capacity will exceed 5 and 4 nm by 2026, becoming the second-largest process node after 28 nm by 2027. TSMC is expanding CoWoS capacity by more than 60% by 2027. The constraint is being addressed gradually, as building a leading-edge fab takes time. SPEAKER_1: The key idea for our listener tracking this chain: the AI trade isn't one stock. It's a sequence of constraints moving through the supply chain. Nvidia was the visible first move. TSMC is the manufacturing layer that converts that demand into physical chips—and it's been the binding constraint at the fabrication and packaging level simultaneously. SPEAKER_2: And that handoff doesn't stop at the foundry. Once the chip is fabricated and packaged, it still needs to be fed data fast enough to actually perform. That's where high-bandwidth memory enters—and where the next bottleneck in this chain lives. The memory layer is running its own shortage, and it's the subject of the next episode. SPEAKER_1: And that handoff to memory is exactly where I want to go next. But before we get there—one thing I keep coming back to from this episode is the scale of TSMC's dominance. Because 67% of foundry revenue among the top ten foundries isn't just a market share number. That's a structural fact about how the global chip industry is organized. SPEAKER_2: It really is. And the way to think about it is that TSMC's dominance keeps compounding precisely because of the capex barrier. Smaller foundries can't justify the multi-billion-dollar investments required for advanced nodes. So the gap between TSMC and everyone else doesn't close—it widens. TrendForce and IDC both describe this as a longer-term structural consolidation, not just an AI cycle effect. SPEAKER_1: So the moat self-reinforces. The more advanced the node, the fewer players can afford to compete. SPEAKER_2: [emphasis] Exactly. And here's the part that's easy to miss: it's not just wafer fabrication anymore. TSMC's own 2024 annual report shows it accounted for about 34% of the broader Foundry 2.0 industry—packaging, testing, mask-making—up from 28% the prior year. That's a company expanding its grip on the entire manufacturing stack, not just the wafer. SPEAKER_1: So when someone talks about securing TSMC capacity, they're not just talking about a wafer slot. They're talking about an integrated manufacturing relationship. SPEAKER_2: Right. And that integration is what makes switching so difficult. Think of a chip designer trying to move a complex AI accelerator to a different foundry. They'd need to re-qualify the process, rebuild the packaging flow, re-verify the yield. That's not a quarter's work. That's years. SPEAKER_1: Mm-hmm. Now, the forward picture—what does capacity expansion actually look like from here? SPEAKER_2: TrendForce projects 3 nm capacity will surpass 5 and 4 nm by end of 2026 and become the second-largest process node after 28 nm by 2027. CoWoS packaging capacity is set to grow more than 60% by 2027. The constraint is being addressed—but the timeline is measured in years, not quarters. You can't build a leading-edge fab fast. SPEAKER_1: Wait—so even with aggressive expansion, the bottleneck persists through most of this decade? SPEAKER_2: [short pause] That's what the data implies. Because chip designs are finalized one to three years in advance, TrendForce observes the current imbalance has effectively locked in a period where TSMC remains the critical constraint at 3 nm and in advanced packaging. Expansion helps at the margin, but demand is also growing. SPEAKER_1: So the key idea for someone tracking this chain: the rerating at the foundry layer isn't just about one good quarter. It's about a structural position that's hard to replicate and slow to dilute. SPEAKER_2: That's the takeaway. And it connects directly to what Counterpoint and TrendForce describe as a supply chain arms race—hyperscalers and chip designers competing for scarce 3 nm wafer slots and CoWoS capacity. When your customers are fighting each other for your output, that's pricing power. Now, the handoff: once the chip is fabricated and packaged, it still needs to be fed data fast enough to perform at scale. That's the memory layer—and it's running its own shortage, which is where the next episode picks up.